The present invention relates generally to integrated circuits, and more particularly to an integrated circuit (IC) bus architecture including a full-swing, clocked, common-gate receiver for fast on-chip signal transmission for application particularly in very large scale integrated circuits (VLSICs), such as microprocessors and the like.
Ever increasing performance demands are being placed on computer circuits, microprocessors and other ICs and VLSICs. ICs and VLSICs are being required to operate at continually increasing clock speeds. More components are being placed on an IC to perform more functions at faster speeds. Component layouts often require that components that need to share information or communicate with one another cannot be located proximal to one another resulting in transmission time delays. This problem is exacerbated by VLSI circuits where signal propagation delays due to long interconnections are increasingly dominating the overall performance of these devices.
One known bus arrangement 100 for on-chip signal transmission is shown in FIG. 1. The bus arrangement 100 includes a static CMOS inverter 102 as a receiver. The inverter 102 is connected to a driver circuit 104 by a circuit interconnect line 106. The driver circuit 104 includes a first N-channel metal oxide semiconductor 108 (NMOS) transistor with one terminal connected to ground and a second terminal connected to a terminal of a second NMOS transistor 110. A third P-channel (PMOS) transistor 112 is connected by one terminal to another terminal of the second transistor 110 and to an input of an inverter 114. The other terminal of the third transistor 112 is connected to Vcc or a supply voltage. The gates of the first NMOS transistor 108 and the third PMOS transistor 112 are connected to a system clock (CLK) and the gate of the second NMOS transistor 110 is connectable to receive an input signal (IN). The output of the inverter 114 is connected to the circuit interconnect line 106. The circuit interconnect line 106 is typically a long, distributed resistive/capacitive (RC) line 106.
Another known bus arrangement 200 for on-chip signal transmission is shown in FIG. 2. The bus arrangement 200 includes a driver circuit 202 similar to that just described with respect to FIG. 1. The driver circuit 202 is coupled to a receiver 204 by a distributed RC line 206. The receiver 204 may be a dynamic inverter with a low trip point. Because the receiver 204 has a lower trip point than the bus arrangement 100 of FIG. 1, the bus arrangement 200 will operate at somewhat faster speeds. The bus arrangement 200, however, does not have the ability to recover data. If for any reason a wrong or false data input signal is sensed by the receiver 204 because of coupling noise or supply voltage noise, there is no ability for data recovery by the receiver 204 to sense a correct or true data input signal. For example, during the evaluation period CLK 2 is high and the input to the receiver 204 is low and should remain low. If some coupling noise or supply voltage noise increases the voltage level at the input to the receiver 204 temporarily such that the receiver 204 senses an erroneous or false high input signal, the receiver 204 will be unable to recover and respond to a correct data input, such as a true low input signal, even if the input returns to a low state during the evaluation period (CLK 2 is high).
FIG. 3 shows another known receiver 300 for use in a bus arrangement for on-chip signal transmission. This receiver 300, however, requires differential input signals at the differential inputs 302 and 304 (IN and IN #). Additionally, the receiver 300 has two clock inputs 306 and 308 (CLK), a sense input 310 (SI) that may be a function of the system clock, and differential outputs 312 and 314 (OUT and OUT #). The differential inputs 302 and 304 of the receiver 300 are coupled to interconnects 316 and 318 that are typically long RC lines interconnecting the receiver 300 with other chip components with which the receiver 300 communicates. The receiver 300 therefore requires multiple interconnect lines to other on-chip components and has a rather complex circuit topology. The multiple interconnect lines and the complex circuit topology requires that the receiver 300 occupy a substantially larger portion of vital real estate on a chip and will have a higher power consumption compared to the less complex circuitry of the bus arrangements 100 and 200 in FIGS. 1 and 2.
While the bus arrangement or receiver 300 of FIG. 3 has a much more complex circuit topology compared to the bus arrangements 100 and 200 of FIGS. 1 and 2, the bus arrangement 300 will respond well to small input voltages and provides faster operation and better performance.
The receiver 300, however, also suffers from the ability to recover data after a false input signal. If for any reason a wrong or erroneous data input is sensed by the receiver 300 during an evaluation period, such as an erroneous signal resulting from coupling noise or supply voltage noise, the receiver 300 will have difficulty or be unable to recover or reset to sense a correct or true data input during the same evaluation period. This is because the receiver 300 has a latching action. For example, during a pre-charge time or period (CLK is low and S1 is low), the inputs 302 and 304 are pre-charged to a high state along with the outputs 312 and 314. During the evaluation time or sensing period (CLK is high and S1 is high), an erroneous signal may result in one of the outputs 312 or 314 being sensed and latched to a low state while the other output 312 or 314 remains latched to a high state. Hence if the sensed output 312 or 314 is incorrect, there will be no way for the receiver 300 to recover or reset to sense the correct or true data as the receiver 300 is latched independently of the signals on the inputs 302 and 304.
Accordingly, for the reason stated above, and for other reasons that will become apparent upon reading and understanding the present specification, there is a need for an integrated circuit bus architecture including a receiver for faster on-chip signal transmission than has been previously achievable and that has the ability to recover after a false or erroneous input signal. Additionally, a need exists for a receiver that is single-ended, not requiring differential signals and hence requiring less interconnect routing and consumes less power, and for a receiver that can respond to small input voltages developed at the interconnect or input to the receiver to provide fast conversions or transitions and thereby reduce interconnect-delay of the total bus delay. A need further exists for a receiver that has a simple circuit topology and that requires less design effort.